1. Field of the Disclosure
The present disclosure relates generally to integrated circuit memories, and more particularly to a memory having a low power read cycle and fast access timing.
2. Description of the Related Art
With today's information systems, it is preferable to minimize the power consumed by a memory device utilized in the information system. A low power memory device is especially desirable in battery powered systems or systems susceptible to over-heating. Another desirable feature for memory devices is reduced access time. Reducing the access time of a memory device enables a system utilizing the memory device to operate at faster speeds. However, these two desirable features are in conflict with each other. For example, in conventional memory devices, reducing power consumption typically increases the memory access time.
Providing a memory device that consumes less power and has fast access times is further complicated when providing compilable memory. Compilable memory refers to a memory module provided, for example, in a computer aided design (CAD) environment that allows a designer to select a physical size of a memory array during the design of an application specific integrated circuit (ASIC). Because an implemented memory module can vary in physical size, for example from 256 words to 64 k words, the memory module should advantageously scale access times appropriately. What is desirable is a memory device that is low power, has fast access times and can be efficiently provided as compilable memory.
The use of the same reference symbols in different drawings indicates similar or identical items.